1. Field of the Invention
The present invention relates CMOS device fabrication and more particularly to a CMOS transistor and fabrication method which provides an elevated source-drain structure with narrow gate-to-contact spacing.
2. Description of the Background Art
Elevated source-drain structures have been utilized within CMOS transistors to reduce the series resistance of the device when utilized with either a thicker contact or thicker silicide, or combination thereof, than utilized in conventional CMOS devices. However, current elevated source-drain CMOS transistors require a gate-to-contact spacing of between approximately one-third micron to one micron (0.3to 1.0micron) to reduce the formation of contact holes through the nitride spacer. Providing a method for safely reducing gate-to contact spacing within the elevated source-drain CMOS device can allow circuit density to be increased. In a traditional approach, the source and drain are raised by selective epitaxy after dielectric spacer formation. The width of the spacer (normally, nitride), along with the lithography overlay, sets the minimum limit of gate to contact spacing.
Therefore, a need exists for an elevated source-drain CMOS transistor structure and fabrication method that can provide narrow gate-to-contact spacing for creating enlarged contact junctions. The present invention satisfies that need as well as others, and overcomes the deficiencies of previously developed solutions.
The present invention describes an elevated source-drain CMOS transistor and an associated fabrication process that can reduce gate-to-contact spacing. The method utilizes L-shaped dielectric spacers formed adjacent the gate stack to aid in controlling implantation depth while providing insulation which can reduce the necessary gate-to-contact spacing. The gate to contact spacing is often referred to as xe2x80x9clocal interconnectxe2x80x9d (LI) distance. After formation of the L-shaped spacers, amorphous silicon (a-Si) is formed over the surface of the substrate which preferably covers the lower portion of the L-shaped spacers surrounding the gate stack. Portions of the junction are then extended into the new layer of silicon with deep source-drain dopant implantation. By utilizing the L-shaped spacers, the amount of dopant extension near the junction is restricted, while unabated extension in adjacent source and drain areas within the deposited silicon layer is allowed. The substrate is preferably annealed prior to the formation of silicide in the contact areas of the source, drain, and gate. The L-shaped spacer insulates the central portion of the source-drain channel, such that silicide may be formed over the entire exposed region of deposited amorphous silicon. It will be appreciated that the resultant silicide will be positioned a distance from the gate stack equivalent to the thickness of the deposited first dielectric layer.
An object of the invention is to increase circuit density by narrowing the gate-to-contact spacing within a CMOS transistor.
Another object of the invention is to elevate the source and drain contacts within a CMOS transistor to facilitate the formation of a deeper silicide layer.
Another object of the invention is to provide a fabrication method for a CMOS device with narrow contact distance that may be easily fabricated utilizing conventional processing equipment.
Further objects and advantages of the invention will be brought out in the following portions of the specification, wherein the detailed description is for the purpose of fully disclosing preferred embodiments of the invention without placing limitations thereon.